The present invention relates to an operating operational amplifier, and more particularly, to a folded cascode operating amplifier and an operating method thereof.
In applications involving analog-to-digital converter (ADC) chips, the processing of noise signals is a primary concern. For example, in an ADC or a digital-to-analog converter (DAC), increasing the signal-to-noise ratio (SNR) is regarded as an important design consideration. One of the critical factors influencing the SNR is the transistor flicker noise. Flicker noise is an unwanted energy level that is generated when many dangling bonds appear at the interface between an oxide layer and the silicon substrate in the gate terminal of a transistor. When a charge carrier moves on the interface, some carriers are randomly captured and then released to the energy level to allow the drain terminal current to generate flicker noise. Therefore, reducing the flicker noise in an operational amplifier is a primary design concern.
Enlarging the area of a transistor is one method to reduce flicker noise. The energy associated with the flicker noise is related to the voltage source of the transistor gate terminal. The exact relationship is provided below in the following formula (Razavi, B, “Design of Analog CMOS Integrated Circuits”, pp. 215, McGraw Hill):
            V      n      2        _    =            K                        C          OX                ⁢        WL              ⁢          1      f      
From the above-described formula, it can be induced from the inverse proportionality of WL that the component area must increase as (f) noise signal decreases. Moreover, an accompanying stray capacitance acts to increase the chip power load. Generally, noise from a PMOS transistor is less than that of an NMOS transistor.